1. Technical Field
Embodiments of the present invention generally relate to a semiconductor apparatus, and more particularly, in one or more embodiments, to a buffer circuit of a semiconductor apparatus.
2. Related Art
An electronic device may include a transmission circuit for transmitting current and/or a voltage as a signal and a reception circuit for receiving the signal transmitted from the transmission circuit. The reception circuit may amplify the signal by using a differential amplifier, which is supplied with a power supply voltage.
FIG. 1 is a diagram illustrating the configuration of a known input buffer 10. In FIG. 1, the buffer circuit 10 may include first, second, and third transistors T1, T2, and T3. The third transistor T3 may form the current path of the buffer circuit 10 by receiving a bias voltage BIAS. The first and second transistors T1 and T2 may respectively receive an input signal IN and a reference voltage VREF. When the input signal IN is a high level, since the voltage level of a node A is relatively higher than the voltage level of a node B, the buffer circuit 10 may output an output signal OUT of a high level. Also, when the input signal IN is a low level, since the voltage level of the node A is relatively lower than the voltage level of the node B, the buffer circuit 10 may output the output signal OUT of a low level.
The buffer circuit 10, which amplifies a signal having small current or low voltage level, may be sensitive to a variation in process, voltage and temperature. When the buffer circuit 10 use a power supply voltage VDD as the bias voltage BIAS, because the power supply voltage VDD may vary in its level according to an operating situation of a semiconductor apparatus which includes the buffer circuit 10 therein, the output timing and duty of the output signal OUT outputted from the buffer circuit 10 may become unstable according to a variation in the level of the power supply voltage VDD.